The present invention relates to a semiconductor device having an insulating isolation region and a manufacturing method thereof.
A semiconductor device having in a semiconductor substrate an electrically insulated isolation structure with an effect similar to that of an SOI (Silicon On Insulator) is known. See, for example, JP-A-2001-127149.
FIGS. 11 to 15 are cross sectional views showing a manufacturing method of a semiconductor device, having in a semiconductor substrate an electrically insulated isolation structure with an effect similar to that of an SOI, in the order of manufacturing steps about a principal part of the device. In the following explanations, the character “n” shows that a conduction type is an n-type and the character “p” shows that the conduction type is a p-type.
As the first manufacturing step, as shown in FIG. 11, in a top surface layer of an n-semiconductor substrate 51a, a p-well-region 52 is selectively formed. Moreover, on the top surface layer, a gate insulator film 53 is formed, on which gate electrodes 54 made of polysilicon are formed with one made positioned on the p-well region 52.
Then, as shown in FIG. 12, in the top surface layer of the n-semiconductor substrate 51a, high impurity concentration regions of a p-source region 55, a p-drain region 56 and an n-contact region 57 are formed. Furthermore, in the top surface layer of the p-well region 52, high impurity concentration regions of an n-source region 58, an n-drain region 59 and a p-contact region 60 are formed.
Next to this, as shown in FIG. 13, an interlayer insulator film 61 is formed. The interlayer insulator film 61 is then subjected to patterning and an isolating trench 62 is then formed from the top surface of the n-semiconductor substrate 51a toward inside thereof so as to surround the p-well region 52 and a group of the p-source region 55, the p-drain region 56 and the n-contact region 57. Thus, the top surface layer of the n-semiconductor substrate 51a is partitioned by the isolating trench 62 into partitioned n-semiconductor substrates 51b. Subsequent to this, the isolating trench 62 is filled with insulating material 63 to be formed as insulating isolation region 64.
Following this, as shown in FIG. 14, the top surface of the partitioned n-semiconductor substrate 51b is covered with an unillustrated interlayer insulator film. In the unillustrated interlayer insulator film, contact holes are opened through which metal electrodes are formed as a source electrode 65 electrically connected to the p-source region 55 and the n-contact region 57, a source electrode 67 electrically connected to the n-source region 58 and the p-contact region 60, a drain electrode 66 electrically connected to the p-drain region 56 and a drain electrode 68 electrically connected to the n-drain region 59. The surfaces of the metal electrodes are covered with a cap layer of a material such as polyimide film. The cap layer and the previously explained unillustrated interlayer insulator film are to be included in a film shown in the figure as an interlayer insulator film 69. In succession to this, the back surface of the partitioned n-semiconductor substrate 51b is subjected to cutting to make the partitioned n-semiconductor substrate 51b thinned until the insulating isolation region 64 is exposed. Thus, the partitioned n-semiconductor substrate 51b is divided into a plurality of substrates at the insulating isolation regions 64, by which a plurality of divided n-semiconductor substrates 51c are formed. An assembly of a plurality of the divided n-semiconductor substrates 51c is referred to as an n-semiconductor substrate 51. The insulating material 63 at the bottom of each of the insulating isolation region 64 is made projected from a back surface 70 of the n-semiconductor substrate 51.
Next to this, as shown in FIG. 15, an insulator film 73 is formed on the back surface 70 of the n-semiconductor substrate 51 subjected to cutting to bury the tip 71 of the projected insulating material 63 in the insulator film 73. Finally, the insulator film 73 is adhered to a metal substrate 75 or a ceramic substrate by a conductive adhesive 74 to complete a semiconductor device.
With the insulating material 63 at the bottom of the insulating isolation region 64 made projected and the tip 71 of the projected insulating material 63 made buried in the insulator film 73 in this way, an arrangement can be provided which causes no occurrence of thickness variation and void production, both occurred when an SOI substrate was used, in the insulating material 63 filling the isolating trench 62 with no further occurrence of constricted part in the shape of the isolating trench 62. With thus provided arrangement, reduction in a breakdown voltage can be prevented.
In JP-A-2001-127149, it is also disclosed that characteristics (such as hfe and on-voltage) of a bipolar transistor can be improved by providing a low resistance layer with a material such as metal between the bottom of the n-semiconductor substrate 51 and the insulator film 73. The low resistance layer is formed over the whole back surface 70 of the divided n-semiconductor substrate 51c in the figure. However, it is supposed that the improvement in the characteristics can be also achieved even by partially forming the low resistance layer, though no explanation about this is given in JP-A-2001-127149.
For a method of making the insulating material 63 at the bottom of the insulating isolation region 64 projected from the back surface 70 of the n-semiconductor substrate 51 as described above, there is one in which polishing or etching of the n-semiconductor substrate 51a is carried out by controlling an etching selectivity between the n-semiconductor substrate 51a and the insulating material 63.
However, as shown in FIG. 15, in the structure in which the tip 71 of the insulating material 63 at the bottom of the insulating isolation region 64 projects from the back surface 70 of the n-semiconductor substrate 51, the tip 71 of the projecting insulating material 63 is liable to become a sharpened form after the etching of the back surface of the n-semiconductor substrate 51a. Thus, there is a problem of causing the projecting insulating material 63 to be cracked or chipped in a manufacturing process.
Moreover, in the processing of the back surface 70 of the n-semiconductor substrate 51, mechanical strain (defect layer) sometimes remains in a surface formed by polishing or etching and an interface state sometimes exists at the interface between the back surface 70 of the n-semiconductor substrate 51 and the insulator film 73. When a depletion layer extending in the direction of the back surface 70 of the divided n-semiconductor substrate 51c reaches the back surface 70 of the divided n-semiconductor substrate 51c, a current generated by the remaining mechanical strain and the existence of the interface state causes a leak current to increase, which results in reduction in a breakdown voltage.
Moreover, application of a negative surge voltage to the divided n-semiconductor substrate 51c causes an electric field to concentrate at a corner at which the bottom of the divided n-semiconductor substrate 51c is in contact with the insulating isolation region 64, which sometimes results in reduction in a breakdown voltage.
As shown in FIG. 16, an enlarged view of the section B in FIG. 14, in the structure in which the tip 71 of the insulating material 63 at the bottom of the insulating isolation region 64 projects, the shape of a corner 76 of the divided n-semiconductor substrate 51c in contact with the insulating isolation region 64 becomes convex downward at the polishing of the back surface 70. With such a shape, the electric field concentration at the corer 76 is further intensified to cause remarkable reduction in a breakdown voltage. The insulating material 63 is formed with an oxide film 80 formed on the sidewall of the isolating trench 62 and polyimide 81 filling the isolating trench 62 with the oxide film 80 interposed between.
In view of the above, it would be desirable to provide a semiconductor device in which an excellent breakdown voltage can be obtained and a manufacturing method of the device.